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a
FEATURES Two Matched ADCs on Single Chip 50 MSPS Conversion Speed On-Board Voltage Reference Low Power (<1W) Low Input Capacitance (10 pF) 65 V Power Supplies Flexible Input Range APPLICATIONS Quadrature Demodulation for Communications Digital Oscilloscopes Electronic Warfare Radar
ENCODE AIN
Dual 8-Bit 50 MSPS A/D Converter AD9058
FUNCTIONAL BLOCK DIAGRAM
AD9058
+VREF 8-BIT ANALOGTODIGITAL CONVERTER -VREF +2 V REF
8 A
+VREF 8-BIT ANALOGTODIGITAL CONVERTER -VREF 8 B
ENCODE
GENERAL DESCRIPTION
The AD9058 combines two independent high performance 8-bit analog-to-digital converters (ADCs) on a single monolithic IC. Combined with an optional onboard voltage reference, the AD9058 provides a cost effective alternative for systems requiring two or more ADCs. Dynamic performance (SNR, ENOB) is optimized to provide up to 50 MSPS conversion rates. The unique architecture results in low input capacitance while maintaining high performance and low power (<0.5 watt/channel). Digital inputs and outputs are TTL compatible. Performance has been optimized for an analog input of 2 V p-p ( 1 V; 0 V to +2 V). Using the onboard +2 V voltage reference, the AD9058 can be set up for unipolar positive operation (0 V to +2 V). This internal voltage reference can drive both ADCs. Commercial (0C to +70C) and military (-55C to +125C) temperature range parts are available. Parts are supplied in hermetic 48-lead DIP and 44-lead "J" lead packages.
RF
AIN
QUADRATURE RECEIVER
G
8
Q
90
AD9058
8
G
I
LO
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD9058-SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 1
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . -1.5 V to +2.5 V +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to -6 V2 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +VS Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . .53 mA +VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5 V
-VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5 Operating Temperature Range AD9058JD/JJ/KD/KJ . . . . . . . . . . . . . . . . . . . 0C to +70C Maximum Junction Temperature3 AD9058JD/JJ/KD/KJ . . . . . . . . . . . . . . . . . . . . . . . . +175C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C
ELECTRICAL CHARACTERISTICS
Parameter (Conditions) RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT Input Bias Current Input Resistance Input Capacitance Analog Bandwidth REFERENCE INPUT Reference Ladder Resistance Ladder Tempco Reference Ladder Offset (Top) Reference Ladder Offset (Bottom) Offset Drift Coefficient INTERNAL VOLTAGE REFERENCE Reference Voltage Temperature Coefficient Power Supply Rejection Ratio (PSRR) SWITCHING PERFORMANCE Maximum Conversion Rate4 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) Output Delay (Valid) (tV)4 Output Delay (tV) Tempco Propagation Delay (tPD)4 Propagation Delay (tPD) Tempco Output Time Skew ENCODE INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Pulsewidth (High) Pulsewidth (Low)
[ VS = 5 V; VREF = +2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to +2 V; -VREF = GROUND, unless otherwise noted.]2 All specifications apply to either of the two ADCs
Test Level AD9058JD/JJ Min Typ Max 8 AD9058KD/KJ Min Typ Max 8 0.65 0.8 0.5 1.3 1.4 GUARANTEED 75 12 28 10 175 170 0.45 8 8 50 1.95 1.90 2.0 150 10 50 0.8 0.2 10 8 16 12 -16 1 25 50 0.1 2.20 2.25 1.95 1.90 170 340 12 15 0.25 0.5 0.7 0.5 1.0 1.25 GUARANTEED 75 28 10 175 170 0.45 8 8 50 2.0 150 10 60 0.8 0.2 10 8 16 12 -16 1 25 2.20 2.25 170 340 15 0.25 Unit Bits LSB LSB LSB LSB
Temp
+25C Full +25C Full Full +25C Full +25C +25C +25C +25C Full Full +25C Full +25C Full Full +25C Full Full +25C +25C +25C +25C +25C +25C Full +25C Full +25C Full Full Full Full +25C +25C +25C
I VI I VI VI I VI I IV V I VI V I VI I VI V I VI V I I IV IV V I V I V V VI VI VI VI V I I
A A k pF MHz /C mV mV mV mV V/C V V V/C mV/V MSPS ns ns ps, rms ns ps/C ns ps/C ns V V A A pF ns ns REV. B
120 80
220 270 16 24 23 33
120 80
220 270 16 24 23 33
0.1
1.5 05
1.5 0.5
5
19
2 0.8 600 1000 5 8 8 -2-
2 0.8 600 1000 5 8 8
AD9058
Parameter (Conditions) DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Effective Number of Bits (ENOB)5 Analog Input @ 2.3 MHz @ 10.3 MHz Signal-to-Noise Ratio5 Analog Input @ 2.3 MHz @ 10.3 MHz Signal-to-Noise Ratio5 (Without Harmonics) Analog Input @ 2.3 MHz @ 10.3 MHz 2nd Harmonic Distortion Analog Input @ 2.3 MHz @ 10.3 MHz 3rd Harmonic Distortion Analog Input @ 2.3 MHz @ 10.3 MHz Crosstalk Rejection6 DIGITAL OUTPUTS Logic "1" Voltage (IOH = 2 mA) Logic "0" Voltage (IOL = 2 mA) POWER SUPPLY7 +VS Supply Current -VS Supply Current Power Dissipation Temp +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C Full Full Full Full Full Test Level V V I I I I I I I I I I IV VI VI VI VI VI 2.4 0.4 127 27 770 154 38 960 127 27 770 Min AD9058JD/JJ Typ Max 2 2 7.7 7.4 48 46 48 47 58 58 58 58 60 7.2 7.1 45 44 46 45 48 48 50 50 48 2.4 0.4 154 38 960 AD9058KD/KJ Min Typ Max 2 2 7.7 7.4 48 46 48 47 58 58 58 58 60 Unit ns ns Bits Bits dB dB dB dB dBc dBc dBc dBc dBc V V mA mA mW
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 For applications in which +V S may be applied before -V S, or +V S current is not limited to 500 mA, a reverse biased clamping diode should be inserted between ground and -VS to prevent destructive latch up. See section entitled "Using the AD9058." 3 Typical thermal impedances: 44-lead hermetic J-Leaded ceramic package: JA = 86.4C/W; JC = 24.9C/W; 48-lead hermetic DIP JA = 40C/W; JC = 12C/W. 4 To achieve guaranteed conversion rate, connect each data output to ground through a 2 k pull-down resistor. 5 SNR performance limits for the 48-lead DIP "D" package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with analog input signal 1 dB below full scale at specified frequency. 6 Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT. 7 Applies to both A/Ss and includes internal ladder dissipation. Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
ORDERING GUIDE Temperature Range
0C to +70C
Test Level I - 100% production tested. II - 100% production tested at +25C, and sample tested at specified temperatures. III - Sample tested only. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - All devices are 100% production tested at +25C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
Model
AD9058JJ
Description
Package Option1
J-44 J-44 J-44 D-48 D-48 D-48
44-Lead J-Leaded Ceramic2 AD9058KJ 0C to +70C 44-Lead J-Leaded Ceramic, AC Tested AD9058TJ/8833 -55C to +125C 44-Lead J-Leaded Ceramic, AC Tested AD9058JD 0C to +70C 48-Lead Ceramic DIP AD9058KD 0C to +70C 48-Lead Ceramic DIP, AC Tested AD9058TD/8833 -55C to +125C 48-Lead Ceramic DIP, AC Tested
NOTES 1 D = Hermetic Ceramic DIP Package; J = Leaded Ceramic Package. 2 Hermetically sealed ceramic package; footprint equivalent to PLCC. 3 For specifications, refer to Analog Devices Military Products Databook.
REV. B
-3-
AD9058
PIN DESCRIPTIONS
J-Lead Pin Number ADC-A ADC-B 3 43 4 42 5 41 6 40 7 39 8 38 9 37 10 36 11 35 12-17 34-29 18 28 19 27 20 26 21 25 22 24 COMMON PINS 1 2
GROUND
Name +VREF GROUND +VS AIN -VS -VREF +VS ENCODE D7 (MSB) D6-D1 D0 (LSB) GROUND -VS GROUND +VS COMP +VINT
GROUND
Function Top of internal voltage reference ladder. Analog ground return. Positive 5 V analog supply voltage. Analog input voltage. Negative 5 V supply voltage. Bottom of internal voltage reference ladder. Positive 5 V digital supply voltage. TTL compatible convert command. Most significant bit of TTL digital output. TTL compatible digital output bits. Least significant bit of TTL digital output. Digital ground return. Negative 5 V supply voltage. Analog ground return. Positive 5 V analog supply voltage. Connection for external (0.1 F) compensation capacitor. Internal +2 V reference; can drive +VREF for both ADCs.
GROUND 1 48
Ceramic DIP Pin Number ADC-A ADC-B 14 11 15 10 16 9 17 8 19 6 20 5 22 3 23 2 25 48 26-31 47-42 32 41 21, 24, 33 1, 4, 40 34 39 35 38 36 37 COMMON PINS 12 13
COMP
+VREF
+VREF
+VINT
+VS
+VS
AIN
NC
AIN
6 7 -VS -VREF +VS ENCODE D7 (MSB) D6 D5 D4 D3 D2 D1 17
GROUND +VS -VS GROUND GROUND GROUND D0 (LSB)
40 39 -VS -VREF +VS ENCODE
ENCODE +VS GROUND -VREF -VS NC AIN +VS GROUND +VREF COMP +VINT +VREF GROUND +VS AIN NC -VS -VREF GROUND +VS ENCODE GROUND 24 25
D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) GROUND -VS GROUND +VS +VS GROUND -VS GROUND D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB)
AD9058
TOP VIEW (Not to Scale)
D7 (MSB) D6 D5 D4 D3 D2 GROUND D1 29
D0 (LSB)
+VS
NC
-VS
18
28
NC = NO CONNECT
NC = NO CONNECT
AD9058JJ/KJ Pinouts
+VS
AD9058JD/KD Pinouts
+5.0V
+VS
D0-D7* +VINT
-VREF AIN** ENCODE** +VS +5V -5.2V
13k
+VREF COMP
ENCODE
DIGITAL BITS
0.1 F
AD9058
GROUND
-VS
* INDICATES EACH PIN IS CONNECTED THROUGH 2 k ** INDICATES EACH PIN IS CONNECTED THROUGH 100
AD9058 Equivalent Digital Outputs
AD9058 Equivalent Encode Circuit
AD9058 Burn-In Connections
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
AD9058
THEORY OF OPERATION
ANALOG IN 128 +VREF 127
INTERPOLATING LATCHES
DECODE LOGIC
The AD9058 contains two separate 8-bit analog-to-digital converters (ADCs) on a single silicon die. The two devices can be operated independently with separate analog inputs, voltage references and clocks. In a traditional flash converter, 256 input comparators are required to make the parallel conversion for 8-bit resolution. This is in marked contrast to the scheme used in the AD9058, as shown in Figure 1. Unlike traditional "flash," or parallel, converters, each of the two ADCs in the AD9058 utilizes a patented interpolating architecture to reduce circuit complexity, die size and input capacitance. These advantages accrue because, compared to a conventional flash design, only half the normal number of input comparator cells is required to accomplish the conversion. In this unit, each of the two independent ADCs uses only 128 (27) comparators to make the conversion. The conversion for the seven most significant bits (MSBs) is performed by the 128 comparators. The value of the least significant bit (LSB) is determined by interpolation between adjacent comparators in the decoding register. A proprietary decoding scheme processes the comparator outputs and provides an 8-bit code to the output register of each ADC; the scheme also minimizes error codes. Analog input range is established by the voltages applied at the voltage reference inputs (+VREF and -VREF). The AD9058 can operate from 0 V to +2 V using the internal voltage reference, or anywhere between -1 V and +2 V using external references. Input range is limited to 2 V p-p when using external references. The internal resistor ladder divides the applied voltage reference into 128 steps, with each step representing two 8-bit quantization levels.
ENCODE
256
8
LATCHES
8 8
8
2
-VREF
1
Figure 1. AD9058 Comparator Block Diagram
The onboard voltage reference, +VINT, is a bandgap reference which has sufficient drive capability for both reference ladders. It provides a +2 V reference that can drive both ADCs in the AD9058 for unipolar positive operation (0 V to +2 V). USING THE AD9058 Refer to Figure 2. Using the internal voltage reference connected to both ADCs as shown reduces the number of external components required to create a complete data acquisition system. The input ranges of the ADCs are positive unipolar in this configuration, ranging from 0 V to +2 V. Bipolar input signals are buffered, amplified and offset into the proper input range of the ADC using a good low distortion amplifier such as the AD9617 or AD9618.
1k 74HCT04 50 10pF
10 ENCODE A 8 400 ANALOG IN A 0.5 V 200 - AD9617 800 -2V 0.1F 20k + + AD707 - 20k +2V 2 3 +VINT +VREF A 5 6 AIN A 38
36 ENCODE B 5, 9, 22, 24, 37, 41 18 17 16 15 14 13 12 11
-VREF A -VREF B
+VS
+5V
D0A (LSB)
D7A (MSB)
0.1F 43 +VREF B D0B (LSB) 28 29 30 31 32 33 34 35 7, 20, 26, 39 0.1F 4,19, 21 25, 27, 42
400 ANALOG IN B 0.5 V 200 - AD9617 + 5 0.1F
1
COMP
40
AIN B
D7B (MSB) -VS
AD9058
(J-LEAD)
- 5V 1N4001 (SEE TEXT)
Figure 2. AD9058 Using Internal +2 V Voltage Reference
REV. B
-5-
74HCT 273
800
74HCT 273
CLOCK
CLOCK
AD9058
+5V 1 AD580 2 10k 10k +5V + 0.1F 20k 400 ANALOG IN A 0.125 V 50 - AD9618 + 20k 10 - 1/2 AD708 + 150 2N3906 - 5V 400 ANALOG IN B 0.125 V 50 - AD9618 + 0.1F RZ1, RZ2 = 2,000 SIP (8/PKG) 5k 1 V 40 1 AIN B COMP D7B (MSB) -1V 0.1F 38 -VREF B D0B (LSB) RZ2 28 29 30 31 32 33 34 35 8 5 0.1F +1V 43 1V 6 AIN A +VREF B D0A (LSB) 18 17 16 15 14 13 12 11 RZ1 1/2 AD708 - 150 2N3904 10 3 36 ENCODE B +VS 5, 9, 22, 24, 37, 41 +5V 0.1F 3 1k ENCODE 50k 74ACT04 10pF
10 ENCODE A
+VREF A
74ACT 273 74ACT 273
- 5V 1N4001 (SEE TEXT) 0.1F
8
-VREF A
D7A (MSB)
CLOCK
8
CLOCK -VS 7, 20, 26, 39
AD9058
(J-LEAD) 4,19, 21 25, 27, 42
Figure 3. AD9058 Using External Voltage References
The AD9058 offers considerable flexibility in selecting the analog input ranges of the ADCs; the two independent ADCs can even have different input ranges if required. In Figure 3 above, the AD9058 is shown configured for 1 V operation. The Reference Ladder Offset shown in the specifications table refers to the error between the voltage applied to the +VREF (top) or -VREF (bottom) of the reference ladder and the voltage required at the analog input to achieve a 1111 1111 or 0000 0000 transition. This indicates the amount of adjustment range which must be designed into the reference circuit for the AD9058. The diode shown between ground and -VS is normally reverse biased and is used to prevent latch-up. Its use is recommended for applications in which power supply sequencing might allow +VS to be applied before -VS; or the +VS supply is not current limited. If the negative supply is allowed to float (the +5 V supply is powered up before the -5 V supply), substantial +5 V supply current will attempt to flow through the substrate (VS supply contact) to ground. If this current is not limited to <500 mA, the part may be destroyed. The diode prevents this potentially destructive condition from occurring. Timing Refer to the AD9058 Timing Diagram. The AD9058 provides latched data outputs with no pipeline delay. To conserve power, the data outputs have relatively slow rise and fall times. When designing system timing, it is important to observe (1) set-up and hold times; and (2) the intervals when data is changing. Figure 3 shows 2 k pull-down resistors on each of the D0-D7 output data bits. When operating at conversion rates higher than 40 MSPS, these resistors help equalize rise and fall times and ease latching the output data into external latches. The 74ACT
logic family devices have short set-up and hold times and are the recommended choices for speeds of 40 MSPS or more. Layout To insure optimum performance, a single low-impedance ground plane is recommended. Analog and digital grounds should be connected together and to the ground plane at the AD9058 device. Analog and digital power supplies should be bypassed to ground through 0.1 F ceramic capacitors as close to the unit as possible. An evaluation board (ADI part #AD9058/PCB) is available to aid designers and provide a suggested layout. The use of sockets may limit the dynamic performance of the part and is not recommended except for prototype or evaluation purposes. For prototyping or evaluation, surface mount sockets are available from Methode (part #213-0320602) for evaluating AD9058 surface mount packages. To evaluate the AD9058 in through-hole PCB designs, use the AD9058JD/KD with individual pin sockets (AMP part #6-330808-0). Alternatively, surface mount AD9058 units can be mounted in a through-hole socket (Circuit Assembly Corporation, Irvine California part #CA-44SPC-T). AD9058 APPLICATIONS Combining two ADCs in a single package is an attractive alternative in a variety of systems when cost, reliability and space are important considerations. Different systems emphasize particular specifications, depending on how the part is used. In high density digital radio communications, a pair of high speed ADCs are used to digitize the in-phase (I) and quadrature (Q) components of a modulated signal. The signal presented to each ADC in this type of system consists of message-dependent amplitudes varying at the symbol rate, which is equal to the sample rates of the converters. -6- REV. B
AD9058
N ANALOG INPUT
tA
N+1 N+2
t A = APERTURE TIME tV = DATA DELAY OF
PRECEDING ENCODE
ENCODE
tV
D0 - D 7
VALID DATA FOR N - 1 VALID DATA FOR N VALID DATA FOR N + 1
tPD = OUTPUT PROPAGATION DELAY
t
PD
DATA CHANGING
Figure 4. AD9058 Timing Diagram
Figure 5 below shows what the analog input to the AD9058 would look like when observed relative to the sample clock. Signalto-noise ratio (SNR), transient response, and sample rate are all critical specifications in digitizing this "eye pattern."
ANALOG INPUT
is actual rms error calculated from the converter's outputs with a pure sine wave applied as the input. Maximum conversion rate is defined as the encode (sample) rate at which SNR of the lowest frequency analog test signal drops no more than 3 dB below the guaranteed limit.
60 +125C +25C
HARMONIC DISTORTION - dB
55 -55C 50
SAMPLE CLOCK
Figure 5. AD9058 I and Q Input Signals
45
Receiver sensitivity is limited by the SNR of the system. For the ADC, SNR is measured in the frequency domain and calculated with a Fast Fourier Transform (FFT). The signal-to-noise ratio equals the ratio of the fundamental component of the signal (rms amplitude) to the rms level of the noise. Noise is the sum of all other spectral components, including harmonic distortion, but excluding dc. Although the signal being sampled does not have a significant slew rate at the instant it is encoded, dynamic performance of the ADC and the system is still critical. Transient response is the time required for the AD9058 to achieve full accuracy when a step function input is applied. Overvoltage recovery time is the interval required for the AD9058 to recover to full accuracy after an overdriven analog input signal is reduced to its input range. Time domain performance of the ADC is also extremely important in digital oscilloscopes. When a track (sample)-and-hold is used ahead of the ADC, its operation becomes similar to that described above for receivers. The dynamic response to high-frequency inputs can be described by the effective number of bits (ENOB). The effective number of bits is calculated with a sine wave curve fit and is expressed as: ENOB = N - LOG2 [Error (measured)/Error (ideal)] where N is the resolution (number of bits) and measured error
40
35 30 0.1 1 10 100 INPUT FREQUENCY - MHz
Figure 6. Harmonic Distortion vs. Analog Input Frequency
55
SIGNAL-TO-NOISE RATIO (SNR) - dB
+25C AND +125C 50 8.0
45
7.2
40 -55C 35
6.4
5.5
30 0.1
1
10
100
INPUT FREQUENCY - MHz
Figure 7. AD9058 Dynamic Performance vs. Analog Input Frequency
REV. B
-7-
EFFECTIVE NO. OF BITS (ENOB)
AD9058
MECHANICAL INFORMATION
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead J-Leaded Ceramic (J-44) Package
0.690 0.012 SQ. (17.5 0.305) 0.650 0.008 SQ. (16.51 0.203) PIN 1
48-Lead Hermetic Ceramic DIP (D-48) Package
6
40
48 25
7
39
1 24
0.050 TYP (1.27)
0.225 MAX (5.72 MAX)
2.400 0.024 (60.96 0.609)
0.060 (1.52) 0.015 (0.38)
0.020 TYP (0.508) 17 18 28 0.135 (3.42) MAX 29
0.023 (0.58) 0.014 (0.36)
0.110 (2,79) 0.090 (2.29)
0.70 MAX (1.77 MAX)
0.500 0.008 (12.70 0.203)
0.62 (15.75) 0.59 (12.95)
0.015 (0.38) 0.008 (0.20) 0.017 (0.432) TYP 0.630 0.020 (16.0 0.058) 0.037 0.012 (0.940 0.305) 0.63 (16.00) 0.52 (13.21)
-8-
REV. B
PRINTED IN U.S.A.
0.150 (3.81) MIN
C1474-0-5/00 (rev. B) 00562
Die Dimensions . . . . . . . . . . . . . . . . 106 x 108 x 15 ( 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic) Bond Wire . . . . . . . . . . . . 1-1.3 mil, Gold; Gold Ball Bonding

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